features ? propagation delay of 2.4 ns (typ) ? propagation delay skew <300 ps ? low offset 3 mv ? latch control general description the hcmp96850 is a single, very high speed monolithic comparator. it is pin-compatible with and has improved performance over the ad9685 and the am6685. the hcmp96850 is designed for use in automatic test equip- ment (ate), high speed instrumentation, and other high speed comparator applications. applications ? high speed instrumentation, ate ? high speed timing ? window comparators ? line receivers ? a/d conversion ? threshold detection hcmp96850 single ultrafast voltage comparator block diagram - + noninverting input inverting input gnd 1 v ee gnd 2 v cc latch enable q output q output improvements over other sources include reduced power consumption, reduced propagation delays, and higher input impedance. the hcmp96850 is available in a 16-lead ceramic dip package over the industrial temperature range. it is also available in die form. signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 website: http://www.spt.com e-mail: sales@spt.com
spt 2 3/18/97 hcmp96850 electrical specifications t a = +25 c, v cc = +5.0 v, v ee = -5.2 v, r l = 50 ohms, unless otherwise specified. test test parameters conditions level min typ max units dc electrical characteristics input offset voltage r s = 0 ohms 1 iv -3 +3 mv input offset voltage (v os )r s = 0 ohms, 1 t min spt 3 3/18/97 hcmp96850 electrical specifications t a = +25 c, v cc = +5.0 v, v ee = -5.2 v, r l = 50 ohms, unless otherwise specified. test test parameters conditions level min typ max units output logic levels (ecl 10 kh compatible) output high 50 ohms to -2 v i -.98 -.81 v output low 50 ohms to -2 v i -1.95 -1.63 v ac electrical characteristics 2 propagation delay 10 mv o.d. iii 2.4 3.0 ns latch set-up time iv 0.6 1 ns latch to output delay 50 mv o.d. iv 3 ns latch pulse width v 2 ns latch hold time iv 0.5 ns rise time 20% to 80% v 1.76 ns fall time 20% to 80% v 1.76 ns 1 r s = source impedance. 2 100 mv input step. test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range. test level i ii iii iv v vi
spt 4 3/18/97 hcmp96850 figure 1 - timing diagram t plol latch enable to output low delay - the propagation delay measured from the 50% point of the latch enable signal low to high transition to the 50% point of an output high to low transition. t h minimum hold time - the minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged in order to be acquired and held at the outputs. t pl minimum latch enable pulse width - the minimum time that the latch enable signal must be high in order to acquire an input signal change. t s minimum set-up time - the minimum time before the negative transition of the latch enable signal that an input signal change must be present in order to be acquired and held at the outputs. t pdh input to output high delay - the propagation delay measured from the time the input signal crosses the input reference voltage ( the input offset voltage) to the 50% point of an output low to high transition. t pdl input to output low delay - the propagation delay measured from the time the input signal crosses the input reference voltage ( the input offset voltage) to the 50% point of an output high to low transition. t ploh latch enable to output high delay - the propagation delay measured from the 50% point of the latch enable signal low to high transition to 50% point of an output low to high transition. v od voltage overdrive - the difference between the differential input and reference input voltages. switching terms (refer to figure 1) timing information the timing diagram for the comparator is shown in figure 1. the latch enable (le) pulse is shown at the top. if le is high in the hcmp96850, the comparator tracks the input differ- ence voltage. when le is driven low, the comparator out- puts are latched into their existing logic states. the leading edge of the input signal (which consists of a 10 mv overdrive voltage) changes the comparator output 50% v ref ? os 50% 50% t plol t ploh t pl t s t pdl t pdh v in +=100 mv (p-p), v od =10 mv latch enable differential input voltage output q output q t h v od the set-up and hold times are a measure of the time required for an input signal to propagate through the first stage of the comparator to reach the latching circuitry. input signal changes occurring before t s will be detected and held; those occurring after t h will not be detected. changes between t s and t h may or may not be detected. after a time of t pdl or t pdh (q or q ). the input signal must be maintained for a time t s (set-up time) before the latch enable falling edge and held for time t h after the falling edge for the comparator to accept data. after t h , the output ignores the input status until the latch is strobed again. a minimum latch pulse width of t pl is needed for strobe operation, and the output transitions occur after a time of t ploh or t plol .
spt 5 3/18/97 hcmp96850 typical interface circuit a typical interface circuit using the comparator is shown in figure 3. although it needs few external components and is easy to apply, there are several considerations that should be noted to achieve optimal performance. the very high operating speeds of the comparator require careful layout, decoupling of supplies, and proper design of transmission lines. since the hcmp96850 comparator is a very high frequency and high gain device, certain layout rules must be followed to avoid spurious oscillations. the comparator should be soldered to the board with component lead lengths kept as short as possible. a ground plane should be used, while the input impedance to the part is kept as low as possible, to decrease parasitic feedback. if the output board traces are longer than approximately one-half inch, microstripline tech- niques must be employed to prevent ringing on the output waveform. also, the microstriplines must be terminated at the far end with the characteristic impedance of the line to prevent reflections. all voltage supply pins should be de- coupled with high-frequency capacitors as close to the device as possible. all ground pins and no connects should be connected to a common ground plane to further improve noise immunity. on the hcmp96850, all outputs, whether used or unused, should have identical terminations to minimize ground cur- rent switching. noninverting input inverting input .1 f . 1 f -2 v pulldown + - le = represents line termination. v cc v ee 50 w 50 w gnd 2 gnd 1 v ref v in q outpu t q outpu t r l figure 2 - internal function diagram ref1 ref 2 v ee v cc clk buf le latch ecl out pre amp + - v in v in q gnd 1 gnd 2 general information the hcmp96850 is an ultrahigh speed single voltage com- parator. it offers tight absolute characteristics which guaran- tee matching from package to package. the device has differential analog inputs and complementary logic outputs compatible with ecl systems. the output stage is adequate for driving terminated 50 ohm transmission lines. the hcmp96850 has one latch enable control and should be driven by standard ecl logic levels. it also has two separate ground pins, one for the output to accommodate large ground currents without affecting the rest of the circuit, while the other is for the small signal intermediate stages. the input stage is referenced to v cc and v ee . figure 3 - typical interface circuit
spt 6 3/18/97 hcmp96850 q 22 q 21 4.5 ma v 1 q output q output q 23 q 24 r 8 240 w r 7 240 w v 2 figure 4 - equivalent input circuit figure 5 - output circuit notes: 1. all bnc & semirigid coax shield are grounded. 2. all resistors 1% (10 w = 49.9 w ). 3. keep all leads as short as possible with electrical lengths l1 = l2 + l3. 4. d.u.t. plugs into a 16 pin high frequency pin socket. 5. monitor input impedance 50 w to gnd. 6. semirigid coax shield should be connected as close to the device as possible. figure 6 - test load 50 w coax 50 w r z v pd (-4.0 v) 100 w r l 100 w r z figure 7 - ac test fixture semi rigid semi rigid semi rigid semi rigid dut 0.1 m f 0.1 m f 15 m f 50 w 16.7 w 100 w 50 w 6 6 semi rigid 15 m f l1 l2 l2 l1 l3 4 v+ v- + - le v in - v in + v in + monitor v cc (+5.0v) 16.7 w 16.7 w 50 w 16.7 w 16.7 w 16.7 w 66 q q 6 q 3 r 2 r 1 v cc v in r in v in v r2 v r1 v ee r 3 r 4 r 5 q 2 q 6 q 8 q 5 q 7 q 1 q 4 in 1pf c in 1pf c 100 w 100 w r in
spt 7 3/18/97 hcmp96850 figure 8 - hcmp96850 with hysteresis 100 w -5.2 v v le 0.1 f 300 w v o v in noninverting input inverting input .1 f . 1 f -2 v pulldown + - le hysteresis is obtained by applying a dc bias to the le pin. vle = -1.3 v 100 mv = represents line termination. v cc v ee 50 w 50 w gnd 2 gnd 1 v ref v in q output q output r l package outline 16-lead cerdip inches millimeters symbol min max min max a 0.005 0.13 b 0.200 5.08 c 0.125 0.150 3.18 3.81 d 0.015 0.023 0.38 0.58 e 0.090 0.110 2.29 2.79 f 0.030 0.065 0.76 1.65 g0 15 0 15 h 0.008 0.015 0.20 0.38 i 0.290 0.320 7.37 8.13 j 0.250 0.310 6.35 7.87 k 0.140 0.200 3.56 5.08 l 0.015 0.050 0.38 1.27 m 0.745 0.785 18.92 19.94 n 0.015 0.050 0.38 1.27 e f k l b c d 1 16 a m n g h i j
spt 8 3/18/97 hcmp96850 pin assignments ordering information part number temperature range package type hcmp96850sid -25 to +85 c 16-lead cerdip hcmp96850scu +25 c die* *please see the die specification for guaranteed electrical performance. 1 2 3 16 15 14 4 5 6 7 89 10 11 12 13 gnd 1 16 lead dip v +in -in n/c le n/c v cc ee n/c n/c q q n/c n/c n/c gnd 2 out out pin functions name function gnd 1 circuit ground v cc positive supply voltage +in noninverting input -in inverting input n/c no connection le latch enable v ee negative supply voltage q out output q out inverted output gnd 2 output ground signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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